This year with assistance from RISC-V Foundation we are able to hold “RISC-V Day 2017 Tokyo” in Japan. You might have heard that RISC-V promotes an open RISC CPU architecture for which one can use its Instructions (ISA) for free to promote more innovations, promote more active silicon designs and finally sustaining a computer architecture for 50 years and beyond. SHC (Software Hardware & Consulting LLC) will be the host for this event.
“RISC-V Day” is the first attempt in the world. The background for this 1 day format is to include not only a handful of RISC CPU experts but also others who use the RISC-V processors. RISC-V is a “seed” of silicon innovation which deregulates RISC CPU and its surrounding system. I am hoping that RISC-V “seed” will grow roots and democratize everything surrounding RISC CPU, IP businesses, peripheral logics, analog technologies, and services yielding more productive semiconductor industry in general. RISC-V Workshop has 3 day format and contents are deep and wide. On the other hand only few people are lucky enough to participate these events. The work shop requires a lot of time and company sponsored attendees and people with means can only attend. We would like to make “RISC-V Day” into an event an ordinary application programmers, middle management engineers, start up person with ideas, service provider employees and others can attend. We are soliciting assistance from sponsors to achieve affordable ticket price for the event.
It was only September I heard from RISC-V Chairperson Dr. Krste Asanovic that he can enable a RISC-V meet up in Japan in December, 2017. People who were familiar with event told us that one cannot successfully gather 400 people in December starting from October. On the other hand compared to US, Korea, China, Taiwan and India, we feared that we get behind on RISC-V matters and decided to take a huge risk to hold this conference by booking a large facility Ito Hall of University of Tokyo. RISC-V Workshop started in 2015 and held in West Coast and East Coast of USA. This spring RISC-V Workshop went to Shanghai. There will be a Workshop in November 28-29 in West Coast again. Workshop in China was hosted by nVidia. Since SHC was the only member company of RISC-V in Japan, SHC hosts this event in Japan leveraging University of Tokyo campus.
Figure 1. Google Trend Search Result of “RISC-V”
In the past, the ISA use was a proprietary intellectual properties belonging to the corporate which created it. The corporates creates ISAs, then attempt to keep them proprietary as they fund the software, tools, operating systems development in addition to the hardware. RISC-V on the other hand is an open ISA standard to be used by all.
We will welcome visitors from overseas and count on them to come to Tokyo. I would like to thanks to Broad Band Tower, Internet Research Institute, TechanaLye, RISC-V Foundation and other sponsors as they made it possible to hold this event in a comfortable setting with translations. I am very grateful for those individuals made this event possible, Dr. Krste Asanovic, Dr. Hiroshi Fujiwara, Mr. Hiroharu Shimizu, and Mr. Rick O’Connor to name a few of those who help to arrive at a resolve to hold this event. I hope to see you at the event.
Thank you all,