Program

RISC-V Day 2017 Tokyo December 18, 2017 Program
Conference

9:30-18:00 Ito Hall, Ito International Research Center
Reception
18:00-20:00 Capo Pelicano, Med. Experimental Research Bldg. 13F

University of Tokyo Hongo Campus, 7 Chome-3-1 Hongo, Bunkyō, Tokyo 113-0033
Tel: +81-3-3833-3717
Event URL: www.riscv.tokyo
RISC-V URL:www.riscv.org
Objectives: Learn about RISC-V, the free and open instruction set architecture poised to become the standard ISA for all computing platforms for the next 50+ years. This conference enables those who: ① wish to commercialize IoT and AI solutions using FPGA or SoC + software economically and want more degrees of freedom, ② do not think existing microcontroller solutions will suffice, and attempt to accelerate their application algorithms (e.g. IoT and AI) using hardware, ③ would like to design microcontroller systems that will scale not only in Japan but in the global market, and ④ need to deploy 64 or 128-bit microcontroller hardware and software in the most economical manner.
RISC-V features: ① C++14, Java, Python, FORTRAN, C#, Objective C, Ada, and OpenCL lauguage roadmap, ② GNU toolchain, LLVM, and Linux support, ③ full IEEE floating-point unit arithmetics (FPU), ④ memory management unit (MMU), trusted execution environment (work in progress), ⑥ accelerator interface, ⑦ Type-II hypervisor support, ⑧ security, ⑨ in-circuit emulator support, ⑩ patent infringement avoidance through leveraging prioir artifacts.
Time Language Presenter (Affiliation) Program Contents (Subject to Change)
9:30-9:40 Jpn Program Committee Program, Facility, WiFi, Information, etc.
9:40-10:00 Jpn Hiroshi Fujiwara
(Broad Band Tower, IRI CEO/Chairman)
Changes in Semiconductor Industry and Japan’s Role after 4th Industrial Revolution
10:00-10:20 Jpn @msyksphinz
(FPGA Diary Author)
RISC-V Open Source Hardware Report
10:20-11:00 E/J Krste Asanovic
(RISC-V Chairman, SiFive Chief Architect, UCB)
Keynote Speech: Instruction Wants to be Free!
11:00-11:20 Jpn Eiji Kasahara
(Esperanto Technical Member)
Industrial strength high-performance RISC-V processors for energy efficient computing
11:20-11:40 Eng Charlie Su
(Andes Technology CTO)
Taking RISC-V to Mainstream ASIC’s
11:40-11:45 E/J RISC-V Companies offering Booth and Poster 1 Minute Booth / Poster Introduction
11:45-13:00 Lunch
(For campus dining hall please enter before 12:00)
Poster Session / Booth Presentation / Goods & Book Sale
Press Conference 12:00-13:00 Gallery1 B1F (Press Only)
13:00-13:30 Eng Krste Asanovic
(RISC-V Chairman, SiFive Chief Architect, UCB)
32, 64, and 128-bit RISC-V Architecture Development StatusVector Arithmetics, Privlilege Mode, Hyperviser Support
13:30-13:50 Eng Wei Fu
(Redhat Hardware Enablement Team)
RISC-V 64-bit OS Development Status
13:50-14:10 Jpn Akira Tsukamoto
(Previously with Toyota, Linaro, Sony Computer Entertainment)
RISC-V Software Baseline for 32 / 64 / 128-bit CPUs
14:10-14:30 Eng Jack Kang
(SiFive VP of Products and Biz Development)
Introducing SiFive 64-bit and 32-bit RISC-V Products
14:30-14:50 Eng Ted Speers
(Senior Dirctor of Space Poducts Team and Technical Fellow SOC Products Group)
Microsemis RISC-V Softcore Processors
14:50-15:20 Break Poster Session / Booth Presentation / Goods Book Sale
15:20-15:40 Jpn Hideki Sugimoto
(NSITEXE CTO)
Computing for Age of Autonomous Driving:
Hopes and Visions for RISC-V for Heterogeneous Multicore Systems
15:40-16:00 Jpn Masaaki Ideno
(Synopsys Processor Department)
Quantitative Evaluation and Extending RISC-V using Synopsys ASIP Tools
16:10-16:30 Jpn Kazuhito Murai
(Embitek Sales Manager)
SEGGER Software Development Solution for RISC-V
16:30-16:50 Jpn Shumpei Kawasaki
(SHC CEO)
Japan’s History of ISAs
16:50-17:40 Jpn Speakers RISC-V Q&As
17:40-17:50 Jpn Program Committee Moving to Reception at Medical Building 13F
18:00-18:30 Reception at Medical Research Bldg. 13F Capo Pelicano Poster Session / Booth Presentation / RISC-V Goods Sale
18:30-18:40 Jpn Hiroharu Shimizu
(TechanaLye Chief Analyst)
TechanaLye RISC-V Future Forecast
18:40-18:50 Jpn Yasushi Fukunaga
(Senior VP, Head of R&D Center, Nidec)
Miniatuarization of Computing and Its Effect to Industry
18:50-19:00 Jpn Shiro Harada
(University of Tokyo)
Toast Master Talk
19:00-19:10 Jpn Masahiro Goshima
(Professor, National Institute of Informatics)
Computer Architecture and RISC-V
19:10-19:20 TBD TBD
19:20-19:30 Eng Krste Asanovic
(RISC-V Chairman, SiFive Chief Architect, UCB)
RISC-V in 2020s
19:40-19:50 Reception Continues Poster Session / Booth Presentation / Goods & Book Sale
19:50-19:55 Jpn Program Committee Adjorn of Event and Future Announcement
Place: University of Tokyo Ito Hall7-3-1 Hongo, Bunkyo-Ku, Tokyo Japan Zip Code: 113-0033
Registration
: General 4,800 yen (5,000 yen after Dec 15) Student 2,800 yen (3,000 yen after Dec 15)
Reception 3,500 yen (4,000 yen after Dec 15)
To Register go to: www.riscv.tokyo or call 03-3833-3717
Press Contact: riscv.presssupport@swhwc.com or call 03-3833-3717 (Naomi Tsujioka)
Sponsors
① RISC-V Foundation
② TechanaLye
③ SiFive
④ Andes Technology
⑤ Western Digital
⑥ Embitek
⑦ NSITEXE
⑧ Hitachi

⑨ Broad Band Tower
⑩ Internet Research Institute
Affiliates
① JASA (Japan Embedded Systems Technologies Associations)

② IPSJ (Information Processing Society of Japan)
Special Interest Group of Architecture(SIGARC)
Special Interest Group of System LSI Design Technologies(SIGSLDM)
Special Interest Group of System Software and OS (SIGOS)
Product Exhibits: ① Andes ② SiFIve ③ Synopsys ④ Strawberry Canyon
Host:SH Consulting KK (Japan), Software Hardware & Consulting LLC (USA)
Tel: +81-3-3833-3717 (Shumpei Kawasaki)

4-21-1-3004 Shibaura, Minato-Ku, Tokyo, Japan 108-0023

Background: RISC-V is an Instruction Set Architecture (ISA) developed by University of California, Berkeley with assistance of DARPA. Among advantages of RISC-V are the scalability of the architecture covering 32/64/128 bit data length, thanks to DARPA funding most of the architectural features are validated through multiple implementations, and finally and most importantly supported with fundamental software such as compiler, cross tools, libraries, operating systems from day 1. Krste

Objectives: Since 2015, RISC-V Foundation has been holding Workshops in USA and China. There has been significant interest in RISC-V in Japan. Professor Krste Asanovic, the founder and the Chairman of RISC-V Foundation is visiting Japan this December, 2017. We decided to have one day meet up called RISC-V Day 2017 in Tokyo to spend a day to deliver the most updated information on RISC-V primarily to the future “users” of RISC-V.

Place: Ito Hall, University of Tokyo Hongo Campus, 7-3-1 Hongo, Bunkyo-Ku, Tokyo, Japan. Zip Code: 113-0033. Map and Access Conference Facilities.

リスクファイブ会場マップ (1)

Figure 1. Conference Site

スクリーンショット 2017-10-30 1.09.07

Figure 2. Ito Hall Layout

RISC-V Shipment Projection R1

Figure 3. RISC-V Shipment Projection (Source: SHC)